Embodiments of the invention relate generally to semiconductor logic devices and structures and methods for packaging semiconductor logic devices within embedded chip packages.
High performance, high pin count semiconductor logic devices or chips have hundreds or thousands of input/output (“I/O”) pads for signals, power, and ground. FIG. 1 depicts an exemplary prior art semiconductor logic device 10 with signal I/O pads 12, power I/O pads 14, and ground I/O pads 16 arranged for flip chip solder bump attach. As shown, I/O pads 12, 14, 16 have the same pad size or diameter and are arranged in a uniform array on a grid of uniform x-axis pitch and y-axis pitch distributed over the whole surface of the device 10. A skilled artisan will recognize that a typical complex semiconductor logic device such as a microprocessor, applications processor, or graphics processor would have many more I/O pads than illustrated in FIG. 1. As such, semiconductor logic device 10 is depicted with break lines to represent portions of the semiconductor logic device 10 that have been omitted for clarity purposes.
Semiconductor logic devices such as device 10 are generally mounted to a board, substrate, or interconnect structure 18 by flip chip attach to form a flip chip package 20 as shown in FIG. 2. Solder bumps 22 are attached to each I/O pad 12, 14, 16 and reflowed to attach the device 10 to the upper pads 24 of the multi-layer interconnect structure 18. Interconnect structure 18 has multiple interconnect layers 26, each comprising an insulating layer 28, a wiring layer 30, and metallized vias 32 formed through the insulating layer 28. An underfill resin 34 lies between semiconductor logic device 10 and interconnect structure 18 and encapsulates the solder bumps 22 to control coefficient of thermal expansion (CTE) induced solder fatigue. The interconnect layers 26 electrically couple I/O pads 12, 14, 16 to the lower I/O terminals 36 of the multi-layer interconnect structure 18. Solder balls 38 are attached to the lower I/O terminals 36 and are used to interconnect the interconnect structure 18 to an external structure (not shown) such as a mother board.
Typically, high-end semiconductor logic chips have 70 to 85 percent of all I/O pads dedicated to power and ground due to high power/ground current levels in these devices and performance limitations of the solder bumps. Solder bumps have high resistance losses due to their low electrically conductivity and current limitations due to electro-migration susceptibility. This need for high numbers of power and ground I/O pads can force chip designers to increase the size of a high-end chip to a size larger than the design's gate count requires. Larger chips result in fewer chips per wafer and lower wafer level chip yields, which increases the cost of the chip.
For the past five decades, semiconductor processing has evolved to ever smaller minimum feature sizes—from tens of microns fifty years ago to ten to fifteen nanometers today. Smaller feature sizes allow semiconductor designers to design chips with small elements and permit more semiconductor elements, transistors, or gates per unit area, therefore providing more functionally per chip. This semiconductor evolution trend has generally been done in discrete steps defined by the minimum allowable feature size and are called semiconductor wafer fab nodes or semiconductor technology nodes. The 14-nanometer node is now in wide spread production with some high-end devices moving into the 10-nanometer node. These node shrinks are driven by the desire to add more gates or functionality per chip without increasing the physical size of the chip. Moving semiconductor logic device 10 from one semiconductor technology node onto another node with smaller minimum features allows the device to be shrunk to a smaller size, resulting in more devices per wafer and lower device fabrication costs. Redesigning a complex semiconductor logic device designed for fabrication on a 14-nanometer node line for fabrication on a 10-nanometer node line, for example, potentially provides a nearly 50% die size shrink. A move to an even smaller feature size semiconductor node could shrink the device even further.
Despite the ever-evolving push for device miniaturization, many flip chip devices with high I/O pad counts cannot reduce the die size when moving to a smaller feature node because of the minimum pitch allowable on solder bumped flip chip devices. The minimum pad pitch that can be flip chip solder bump attached with a sufficiently high assemble yield is referred to hereafter as the “minimum solderable pitch” and ranges from about 120 microns to about 160 microns depending on a particular assembly houses' individual assembly processes, materials, and capabilities. Flip chip devices with a full array of I/O pads on the minimum solderable pitch have a size that is pad count limited. Thus, reducing the size of semiconductor logic device 10 would require either reduction in the number of power and ground I/O pads, which would lower power and ground conductivity and device performance, or a reduction in the array grid pitch.
Reducing the array grid pitch is particularly problematic in flip chip solder ball attach. In the simplified pad configuration depicted in FIG. 1 for example, the I/O pads 12, 14, 16 are on the minimum solderable pitch. The problems found with a die shrink of a complex logic semiconductor device are best understood by looking at a specific example of device 10. Example A of device 10 is a 900 I/O pad device with a full 30 by 30 array of I/O pads on a 150 micron pitch grid, with a die size of 4.5 mm×4.5 mm. In this example, there are 116 perimeter I/O signal pads all located on the outer row of the 30 by 30 array of pads. Device 10 also has 392 I/O power pads and 392 I/O ground pads all located in the inner rows of the array. A device with an array grid pitch of 150 microns would typically have 60-70 micron diameter I/O pads and an 80-90 micron solder bump diameter. A tighter grid pitch would require smaller I/O pads, smaller solder bumps, and would have lower bump conductivity, higher assembly costs, higher risk of bump-to-bump shorting, and lower solder fatigue compliance. As a result, designers may move a flip chip device that is pad count limited to a smaller semiconductor node to get improved device performance but the die size could not be shrunk without lower assembly yield, lower device reliability and increased costs.
One known technique for reducing pitch below the minimum solderable pitch is to replace the flip chip solder bumps 22 (FIG. 2) with copper pillars formed on the I/O pads 12, 14, 16 of semiconductor logic device 10. A thin layer of solder layer would be applied at the end of the copper pillars, often as a paste, and reflowed to couple the semiconductor logic device 10 to the interconnect structure 18. While copper pillars can be used on a tighter pitch than the minimum solderable pitch without causing a pad-to-pad short, shrinking the pitch of a copper pillar/solder layer flip chip attach structure increases the risk of electro-migration failures.
Another approach to addressing the performance limitations of flip chip and copper pillar interconnections is to embed logic devices into an organic substrate and form a build-up structure over the chip. U.S. Pat. No. 8,163,596 discloses an embedded chip module that bonds a semiconductor chip under an organic interconnect structure and encapsulates the chip in an organic molding material. The interconnect structure fans out the I/O pads of the chip to the perimeter region outside of the chip forming a fan-out wafer level device. U.S. Pat. No. 5,946,546 applies an organic interconnect structure of the surface of a semiconductor chip and fans in the chip I/O pads from the perimeter of the chip to an array of pads above the surface of the chip in order to convert a chip designed for wire bond assembly into a device with an area array of I/O terminals configured for flip chip solder bump assembly. The resulting reconfigured device could be flip chip attached onto a board, substrate or package, eliminating wire bonds.
One key problem with utilizing embedded chip packaging is that the interconnect structure built over the chip has a yield loss due to interconnect fabrication defects such as shorts and opens. A defect in the interconnect structure that is formed after a chip is embedded in the structure would cause the chip to be scrapped along with the defective interconnect structure. Yield losses are low (1-2%) in embedded chip packages that incorporate non-complex, low I/O count chips. Complex semiconductor logic devices with high numbers of I/O pads, on the other hand, require complex interconnect structures with unacceptable yield losses of 20% or higher. A 20% embedded chip yield loss would cause 20% of the complex chips to be scrapped with the defective interconnect structures in which they are embedded. For these reasons, the implementation of embedded chip technologies to complex semiconductor logic devices has been restricted and has not been done in high volume manufacturing.
Accordingly, there is a need for a miniaturized semiconductor logic device that addresses the above limitations and can be packaged using embedded chip technologies with low interconnect yields.